As recent rapid trend in modern electronic devices is not only toward lighter and smaller devices, but also toward multi-function and high-performance devices, the integrated-circuit (IC) fabrication and technology has to evolve correspondingly toward a more high-density and miniature design so as to allow more electronic components to be received inside limited chip space. Consequently, the relating IC package structure and the package technology are evolved accordingly to meet the trend.
Conventionally, a wafer-level packaging (WLP) process can be illustrated in FIG. 1A-1C. At first, an adhesive layer 18 is formed on a wafer carrier 11 as shown in FIG. 1A. Next, a semiconductor die 13 and an electronic component 15 with their connection terminals 16 at the bottoms are bonded onto the carrier 11 through the adhesive layer 18, and then a molding compound 12 is formed on the carrier 11 to cover the semiconductor die 13 and the electronic component 15 to be a package unit as shown in FIG. 1B. After the carrier 11 and the adhesive layer 18 is removed, the semi-finished package structure 20 is turned over and a redistribution layer (RDL) 17 is then formed on the upper surface 21 of the semi-finished package structure 20 as shown in FIG. 1C.
It is difficult to fabricate a fine-pitch-wiring RDL 17 by a conventional photolithography means, because fine-pitch wires can be realized only if the upper surface 21 of the semi-finished package structure 20 is very flat. However, to achieve the high surface flatness, a costly adhesive is needed as the adhesive layer 18 and the semiconductor die 13 and the electronic component 15 have to be bonded onto the adhesive layer 18 in a slow and precise way, which would increase the fabrication cost. Therefore, it is in need of a new and advanced packaging solution to reduce the fabrication cost.